The fabrication of integrated circuits is an extremely complex process that may involve hundreds of individual operations. Essentially, the process includes the diffusion of precisely predetermined amounts of dopant material into precisely predetermined areas of a silicon wafer to produce active devices such as transistors. This is typically done by utilizing a photomask and photoresist to define a pattern of areas into which diffusion is to occur through the openings in the photoresist or through openings in a film defined by the photoresist.
After a predetermined number of such diffusion operations have been carried out to produce the desired number of transistors in the wafer, they are interconnected as required by interconnection lines. These interconnection lines, or interconnects as they are also known, are typically formed by deposition of an electrically conductive material which is defined into the desired interconnect pattern by a photomask, photoresist and etching process or is deposited into openings in an insulator film and then planarized. A typical completed integrated circuit may have millions of transistors contained within a 0.1 inch by 0.1 inch silicon chip and interconnects of submicron dimensions.
In view of the device and interconnect densities required in present day integrated circuits, it is imperative that the manufacturing processes be carried out with utmost precision and in a way that minimizes defects and maximizes parametric control. For reliable operation, the electrical characteristics of the circuits must be kept within carefully controlled limits, which implies a high degree of control over the myriad of operations and fabrication processes. For example, in the photoresist and photomask operations, the presence of contaminants such as dust, minute scratches and other imperfections in the patterns on the photomasks can produce defective patterns on the semiconductor wafers, resulting in defective integrated circuits. Further, defects can be introduced in the circuits during the diffusion operations themselves. Defective circuits may be identified both by visual inspection under high magnification and or by electrical tests. Once defective integrated circuits have been identified, it is desired to take steps to decrease the number of defective integrated circuits produced in the manufacturing process, thus increasing the yield of the integrated circuits meeting specifications.
Semiconductor technologies beyond 130 nm have high levels of leakage currents. For example, for a 130 nm technology node, leakage components of chip power may be about 10 to about 20 percent of total power. As the technologies get smaller, the observed leakage currents become higher and less predictable. At 90 nm, the leakage currents may dissipate about 25 to about 50 percent of total power and at 65 nm, the leakage currents may dissipate about 25 to about 65 percent of total power. Some semiconductor products require tighter leakage and better performance than the base technology can provide. In these cases, test screens are used to narrow the distribution around a nominal device.
A contemporary process for setting up a test screen includes proposing a screen of a statistical deviation from a nominal chip speed using, for example, IDDQ measurements for leakage current and/or a ring oscillator or scan chain measurements for performance. Peformance testing is well established and easier to implement than leakage current testing. Leakage currents are generally measured using IDDQ testing. IDDQ testing relies on measuring the supply current (Idd) in the quiescent state when the devices are idle and not switching. Fault-free CMOS devices consume very little current while in the quiescent state with the clock stopped. In contrast, many common manufacturing faults will cause the observable leakage current of defective devices to increase by orders of magnitude, which can increase the sensitivity of IDDQ testing.
From these types of measurements and knowledge of the technology, manual estimates are performed to determine the circuit limited yield for the test screens, which is then used to determine the yield loss of the chips. The circuit limited yield and yield losses are accounted for when calculating and preparing a quote to a customer. The product is then designed and a manual evalulation is performed to determine whether the quoted criteria was met. If the screen criteria was not met, the customer is requoted and the test screen is manually implemented. Approximately two weeks are required, using this process, to produce a quote for the customer.
What is needed, therefore, is a method to automate and reduce the time for quoting product costs.